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ARM architectured microcontroller reverse engineer
  • ARM architecture introduction
  • The ARM architecture describes a family of RISC-based computer processors designed and licensed by British company ARM Holdings. It was first developed in the 1980s[2] by Acorn Computers Ltd to power their desktop machines and subsequently spun off as a separate company, now ARM Holdings. Globally as of 2013 it is the most widely used 32-bit instruction set architecture in terms of quantity produced.[3][4] According to ARM Holdings, in 2010 alone, producers of chips based on ARM architectures reported shipments of 6.1 billion ARM-based processors, representing 95% of smartphones, 35% of digital televisions and set-top boxes and 10% of mobile computers.[5]

    As an IP core business, ARM Holdings itself does not manufacture its own electronic chips, but licenses its designs to other semiconductor manufacturers. ARM-based processors and systems on a chip include the Qualcomm Snapdragon, nVidia Tegra, Marvell Xscale and Texas Instruments OMAP, as well as ARM's Cortex series and Apple System on Chips (used in its iPhones). The name was originally an acronym for Acorn RISC Machine [6] and subsequently, after the name Acorn was dropped, Advanced RISC Machine.

    Using a RISC based approach to computer design, ARM processors require significantly fewer transistors than processors that would typically be found in a traditional computer. The benefits of this approach are reduced costs, heat and power usage compared to more complex chip designs, traits which are desirable for light, portable, battery-powered devices such as smart phones and tablet computers.[7] The reduced complexity and simpler design allows companies to build a low-energy system on a chip for an embedded system incorporating memory, interfaces, radios, etc. The earliest example was the Apple Newton PDA but this same approach is still used in the Apple A4 and A5 chips in the iPad. Alternatively the use of a simpler design allows more efficient multi-core CPUs and higher core counts at lower cost, allowing higher levels of processing power and improved energy efficiency for servers and laptops and notepad computers.


  • ARM architecture MCU Mikatech can reverse engineer
  • Atmel AT91SAMxxx series:
    AT91SAM9XE512 AT91SAM9XE256 AT91SAM9XE128 AT91SAM7S64B AT91SAM7S32B AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32 AT91SAM7XC512 AT91SAM7XC256 AT91SAM7XC128 AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 AT91SAM7S161 AT91SAM7S512 AT91SAM7S256 AT91SAM7S128 AT91SAM7S64 AT91SAM7S321 ...
  • Atmel AT91SAMxxx series:
    LPC1769 LPC1768 LPC1767 LPC1766 LPC1765 LPC1764 LPC1759 LPC1758 LPC1756 LPC1754 LPC1752 LPC1751 LPC1343 LPC1342 LPC1313 LPC1311 LPC1114 LPC1113 LPC1112 LPC1111 LPC2106 LPC2109 LPC2114 LPC2119 LPC2124 LPC2129 LPC2131 LPC2132 LPC2134 LPC2136 LPC2138 LPC2141 LPC2142 LPC2144 LPC2146 LPC2148 LPC2194 LPC2212 LPC2214 LPC2292 LPC2294 LPC2364 LPC2366 LPC2368 LPC2378 LPC1102 LPC1104 LPC1110 LPC1111/002 LPC1111/101 LPC1111/102 LPC1111/103 LPC1111/201 LPC1111/202 LPC1111/203 LPC1112/101 LPC1112/102 LPC1112/103 LPC1112/201 LPC1112/202 LPC1112/203 LPC1113/201 LPC1113/202 LPC1113/203 LPC1113/301 LPC1113/302 LPC1113/303 LPC1114/102 LPC1114/201 LPC1114/202 LPC1114/203 LPC1114/301 LPC1114/302 LPC1114/303 LPC1114/323 LPC1114/333 LPC1115/303 LPC11A02 LPC11A04 LPC11A11/001 LPC11A12/101 LPC11A13/201 LPC11A14/301 LPC11C12/301 LPC11C14/301 LPC11C22/301 LPC11C24/301 LPC11D14/302 LPC11E11/101 LPC11E12/201 LPC11E13/301 LPC11E14/401 LPC11E36/501 LPC11E37/501 LPC11U12/201 LPC11U13/201 LPC11U14/201 LPC11U23/301 LPC11U24/301 LPC11U24/401 LPC11U34/311 LPC11U34/421 LPC11U35/401 LPC11U35/501 LPC11U36/401 LPC11U37/401 LPC11U37/501 LPC1224 LPC1225 LPC1226 LPC1227 LPC12D27 LPC1311 LPC1313 LPC1315 LPC1316 LPC1317 LPC1342 LPC1343 LPC1345 LPC1346 LPC1347 LPC1751 LPC1752 LPC1754 LPC1756 LPC1758 LPC1759 LPC1763 LPC1764 LPC1765 LPC1766 LPC1767 LPC1768 LPC1769 LPC1772 LPC1774 LPC1776 LPC1777 LPC1778 LPC1785 LPC1786 LPC1787 LPC1788 LPC4072 LPC4074 LPC4076 LPC4078 LPC4088 LPC810 LPC811 LPC812 LPC1800 LPC1810 LPC1820 LPC1830 LPC1850 LPC1853 LPC1857 LPC2000 LPC2101 LPC2102 LPC2103 LPC2104 LPC2105 LPC2106 LPC2109 LPC2114 LPC2119 LPC2124 LPC2129 LPC2131 LPC2132 LPC2134 LPC2136 LPC2138 LPC2141 LPC2142 LPC2144 LPC2146 LPC2148 LPC2157 LPC2158 LPC2194 LPC2210 LPC2212 LPC2214 LPC2220 LPC2290 LPC2292 LPC2294 LPC2361 LPC2362 LPC2364 LPC2365 LPC2366 LPC2367 LPC2368 LPC2377 LPC2378 LPC2387 LPC2388 LPC2420 LPC2458 LPC2460 LPC2468 LPC2470 LPC2478 LPC288x LPC2880 LPC2888 LPC3100 LPC3130 LPC3131 LPC3141 LPC3143 LPC3152 LPC3154 LPC3200 LPC3180 LPC3220 LPC3230 LPC3240 LPC3250 LPC4300 LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357...
  • ST STM32xxx series:
    STM32F100V STM32F101 STM32F103 STM32F105 STM32F107RC STM32L151 STM32L152 STM32F205 STM32F207 STM32F215 STM32F217 STM32F405 STM32F407 STM32F415 STM32F417 STM32L151 STM32L152 STM32F101RE STM32F101RD STM32F205RC STM32F101VE STM32F101VD STM32F100RE STM32F103RE STM32F100VE STM32F100RD STM32F103RD STM32F100VD STM32F103VD STM32F100ZD STM32F205VC STM32F207VC STM32F205ZC STM32F105VC STM32F105RC STM32F101RC STM32F107RC STM32F101VC STM32F107VC STM32F101ZC STM32F100RC STM32F103RC STM32F100VC STM32F103VC STM32F100ZC STM32F205RB STM32L151CB STM32L152CB STM32L151RB STM32L152RB STM32F205VB STM32L15VB STM32F105VB STM32L152VB STM32F103ZC STM32F103TB STM32F101CB STM32F103CB STM32F101RB STM32F103RB STM32F101VB STM32F107VB STM32F101TB STM32F100CC STM32F102CB STM32F100RB STM32F102RB STM32F100VB STM32F103VB STM32L151C8 STM32L152C8 STM32F103C8 STM32F102C8 STM32L152C6 STM32F103C6 STM32F102C6 STM32F103C4 STM32F102C4 STM32L151R8 STM32F105R8 STM32F103T8 STM32F101T8 STM32F101C8 STM32F100C8 STM32L151C6 STM32F101R8 STM32F100R8 STM32L151R6 STM32F101R6 STM32F100R6 STM32F101R4 STM32F100R4 STM32F407VG STM32F417VG STM32F407ZG STM32F417ZG STM32F405RG STM32F415RG STM32F405VG STM32F415VG STM32F405ZG STM32F415ZG STM32F207VG STM32F217VG STM32F207ZG STM32F217ZG STM32F205RG STM32F215RG STM32F205VG STM32F215VG STM32F205ZG STM32F215ZG STM32F101RG STM32F103RG STM32F101VG STM32F103VG STM32F101ZG STM32F103ZG STM32F205RF STM32F101RF STM32F103RF STM32F205VF STM32F101VF STM32F407VE STM32F207VE STM32F207VF STM32F103VF STM32F417VE STM32F217VE STM32F215VE STM32F103VE STM32F205ZF STM32F101ZF STM32F407ZE STM32F207ZE STM32F205ZE STM32F101ZE STM32F100ZE STM32F101ZD STM32F103ZD STM32F207ZC STM32F207IC STM32F103VE STM32F207ZF STM32F103ZF STM32F417ZE STM32F217ZE STM32F215ZE STM32F407IE STM32F207IE STM32F417IE STM32F217IE STM32F207IF STM32F207IG STM32F217IG STM32F407IG STM32F417IG STM32F205RE STM32F215RE STM32F205VE ...

  • List of ARM microprocessor cores
  • ARM Holdings' microprocessor cores are listed here, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

    ARM microprocessor cores[edit source | edit]Designed by ARM[edit source | edit]ARM Family ARM Architecture ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz
    ARM1 ARMv1 ARM1 First implementation None
    ARM2 ARMv2 ARM2 ARMv2 added the MUL (multiply) instruction None 4 MIPS @ 8 MHz
    0.33 DMIPS/MHz
    ARMv2a ARM250 Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions. None, MEMC1a 7 MIPS @ 12 MHz
    ARM3 ARMv2a ARM3 First integrated memory cache. 4 KB unified 12 MIPS @ 25 MHz
    0.50 DMIPS/MHz
    ARM6 ARMv3 ARM60 ARMv3 first to support 32-bit memory address space (previously 26-bit) None 10 MIPS @ 12 MHz
    ARM600 As ARM60, cache and coprocessor bus (for FPA10 floating-point unit). 4 KB unified 28 MIPS @ 33 MHz
    ARM610 As ARM60, cache, no coprocessor bus. 4 KB unified 17 MIPS @ 20 MHz
    0.65 DMIPS/MHz
    ARM7 ARMv3 ARM700 8 KB unified 40 MHz
    ARM710 As ARM700, no coprocessor bus. 8 KB unified 40 MHz
    ARM710a As ARM710 8 KB unified 40 MHz
    0.68 DMIPS/MHz
    ARM7TDMI ARMv4T ARM7TDMI(-S) 3-stage pipeline, Thumb none 15 MIPS @ 16.8 MHz
    63 DMIPS @ 70 MHz
    ARM710T As ARM7TDMI, cache 8 KB unified, MMU 36 MIPS @ 40 MHz
    ARM720T As ARM7TDMI, cache 8 KB unified, MMU with Fast Context Switch Extension 60 MIPS @ 59.8 MHz
    ARM740T As ARM7TDMI, cache MPU
    ARM7EJ ARMv5TEJ ARM7EJ-S 5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructions none
    ARM8 ARMv4 ARM810[4][5] 5-stage pipeline, static branch prediction, double-bandwidth memory 8 KB unified, MMU 84 MIPS @ 72 MHz
    1.16 DMIPS/MHz
    ARM9TDMI ARMv4T ARM9TDMI 5-stage pipeline, Thumb none
    ARM920T As ARM9TDMI, cache 16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension)[6] 200 MIPS @ 180 MHz
    ARM922T As ARM9TDMI, caches 8 KB/8 KB, MMU
    ARM940T As ARM9TDMI, caches 4 KB/4 KB, MPU
    ARM9E ARMv5TE ARM946E-S Thumb, Enhanced DSP instructions, caches variable, tightly coupled memories, MPU
    ARM966E-S Thumb, Enhanced DSP instructions no cache, TCMs
    ARM968E-S As ARM966E-S no cache, TCMs
    ARMv5TEJ ARM926EJ-S Thumb, Jazelle DBX, Enhanced DSP instructions variable, TCMs, MMU 220 MIPS @ 200 MHz
    ARMv5TE ARM996HS Clockless processor, as ARM966E-S no caches, TCMs, MPU
    ARM10E ARMv5TE ARM1020E 6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP) 32 KB/32 KB, MMU
    ARM1022E As ARM1020E 16 KB/16 KB, MMU
    ARMv5TEJ ARM1026EJ-S Thumb, Jazelle DBX, Enhanced DSP instructions, (VFP) variable, MMU or MPU
    ARM11 ARMv6 ARM1136J(F)-S[7] 8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructions variable, MMU 740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
    ARMv6T2 ARM1156T2(F)-S 8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructions variable, MPU
    ARMv6Z ARM1176JZ(F)-S As ARM1136EJ(F)-S variable, MMU + TrustZone 965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors[8]
    ARMv6K ARM11 MPCore As ARM1136EJ(F)-S, 1–4 core SMP variable, MMU
    SecureCore ARMv6-M SC000 0.9 DMIPS/MHz
    ARMv4T SC100
    ARMv7-M SC300 1.25 DMIPS/MHz
    Cortex-M ARMv6-M Cortex-M0 [9] Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory No cache, No TCM, No MPU 0.84 DMIPS/MHz
    Cortex-M0+ [11] Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memory No cache, No TCM, optional MPU with 8 regions 0.93 DMIPS/MHz
    Cortex-M1 [12] Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory No cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, No MPU 136 DMIPS @ 170 MHz,[13] (0.8 DMIPS/MHz FPGA-dependent)[14]
    ARMv7-M Cortex-M3 [15] Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory No cache, No TCM, optional MPU with 8 regions 1.25 DMIPS/MHz
    ARMv7E-M Cortex-M4 [16] Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory No cache, No TCM, optional MPU with 8 regions 1.25 DMIPS/MHz
    Cortex-R ARMv7-R Cortex-R4 [17] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic 0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 8/12 regions
    Cortex-R5 (MPCore) [18] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) [19] 0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 12/16 regions
    Cortex-R7 (MPCore) [20] Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP [19] 0-64 KB / 0-64 KB, ? of 0-128 KB TCM, opt MPU with 16 regions
    Cortex-A ARMv7-A Cortex-A5 [21] Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 4-64 KB / 4-64 KB L1, MMU + TrustZone 1.57 DMIPS / MHz per core
    Cortex-A7 MPCore [22] Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design[23] 32 KB / 32 KB L1, 0-4 MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone 1.9 DMIPS / MHz per core
    Cortex-A8 [24] Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline 16-32 KB / 16-32 KB L1, 0-1 MB L2 opt ECC, MMU + TrustZone up to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
    Cortex-A9 MPCore [25] Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 16-64 KB / 16-64 KB L1, 0-8 MB L2 opt Parity, MMU + TrustZone 2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)
    ARM Cortex-A12 [26] Application profile, ARM / Thumb-2 / DSP / VFPv4 FPU / NEON / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP) 32-64KB / 32 KB L1, 256KB-8 MB L2 3.0 DMIPS / MHz per core
    Cortex-A15 MPCore [27] Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[23] 32 KB / 32 KB L1, 0-4 MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone At least 3.5 DMIPS/MHz per core (Up to 4.01 DMIPS/MHz depending on implementation).[28]
    Cortex-A50 ARMv8-A Cortex-A53[29] Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline 8~64 KB/8~64 KB L1 per core, 128 KB~2 MB L2 shared, 40-bit physical addresses 2.3 DMIPS/MHz
    Cortex-A57[30] Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline 48 KB/32 KB L1 per core, 512 KB~2 MB L2 shared, 44-bit physical addresses At least 4.1 DMIPS/MHz per core (Up to 4.76 DMIPS/MHz depending on implementation).
    ARM Family ARM Architecture ARM Core Feature Cache (I/D), MMU Typical MIPS @ MHz

    Designed by third parties[edit source | edit]These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

    Family ARM Architecture Core Feature Cache (I/D), MMU Typical MIPS @ MHz
    StrongARM ARMv4 SA-1 5-stage pipeline 16 KB/8–16 KB, MMU 133–206 MHz
    1.0 DMIPS/MHz
    Faraday[31] ARMv4 FA510 6-stage pipeline up to 32 KB / 32 KB Cache, MPU 1.26 DMIPS/MHz
    100-200 MHz
    FA526 up to 32 KB / 32 KB Cache, MMU 1.26 MIPS/MHz
    166-300 MHz
    FA626 8-stage pipeline 32 KB/32 KB Cache, MMU 1.35 DMIPS/MHz
    500 MHz
    ARMv5TE FA606TE 5-stage pipeline no cache, no MMU 1.22 DMIPS/MHz
    200 MHz
    FA626TE 8-stage pipeline 32 KB/32 KB Cache, MMU 1.43 MIPS/MHz
    800 MHz
    FMP626TE 8-stage pipeline, SMP 1.43 MIPS/MHz
    500 MHz
    FA726TE 13 stage pipeline, dual issue 2.4 DMIPS/MHz
    1000 MHz
    XScale ARMv5TE XScale 7-stage pipeline, Thumb, Enhanced DSP instructions 32 KB/32 KB, MMU 133–400 MHz
    Bulverde Wireless MMX, Wireless SpeedStep added 32 KB/32 KB, MMU 312–624 MHz
    Monahans[32] Wireless MMX2 added 32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMU up to 1.25 GHz
    Sheeva ARMv5 Feroceon 5-8 stage pipeline, single-issue 16 KB / 16 KB, MMU 600-2000 MHz
    Jolteon 5-8 stage pipeline, dual-issue 32 KB / 32 KB, MMU
    PJ1 (Mohawk) 5-8 stage pipeline, single-issue, Wireless MMX2 32 KB / 32 KB, MMU 1.46 DMIPS/MHz
    1.06 GHz
    ARMv6/ARMv7-A PJ4 6-9 stage pipeline, dual-issue, Wireless MMX2, SMP 32 KB / 32 KB, MMU 2.41 DMIPS/MHz
    1.6 GHz
    Snapdragon ARMv7-A Scorpion [33] 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide) 256 KB L2 per core 2.1 DMIPS / MHz per core
    Krait [33] 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide) 4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core 3.3 DMIPS / MHz per core
    Apple Ax ARMv7-A Apple Swift [34] 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON L1: 32 kB instruction + 32 kB data, L2: 1 MB 3.5 DMIPS / MHz Per Core
    X-Gene ARMv8-A X-Gene 64 bit, quad issue, SMP Cache, MMU, Virtualization 3 GHz
    Denver ARMv8-A Parker 64 bit

    See also[edit source | edit] Computer science portal
    Electronics portal
    ARM architecture
    List of applications of ARM cores
    References[edit source | edit]^ "Line Card" (PDF). 2003. Retrieved 2011-01-06.
    ^ ARM Ltd and ARM Germany GmbH. "Device Database". Keil. Retrieved 2011-01-06.
    ^ "Processors". ARM. 2011. Retrieved 2011-01-06.
    ^ ARM Holdings (1996-08-07), ARM810 – Dancing to the Beat of a Different Drum (PDF), Hot Chips .
    ^ "VLSI Technology Now Shipping ARM810". EE Times. August 26, 1996. Retrieved March 16, 2012.
    ^ Register 13, FCSE PID register ARM920T Technical Reference Manual
    ^ "ARM1136J(F)-S – ARM Processor". Arm.com. Retrieved 2009-04-18.
    ^ "ARM11 Processor Family". ARM. Retrieved 2010-12-13.
    ^ Cortex-M0 Specification Summary; ARM Holdings.
    ^ a b c Cortex-M0/M0+/M1 Instruction Set; ARM Holding.
    ^ Cortex-M0+ Specification Summary; ARM Holdings.
    ^ Cortex-M1 Specification Summary; ARM Holdings.
    ^ "ARM Extends Cortex Family with First Processor Optimized for FPGA", ARM press release, March 19, 2007. Retrieved April 11, 2007.
    ^ "ARM Cortex-M1", ARM product website. Retrieved April 11, 2007.
    ^ Cortex-M3 Specification Summary; ARM Holdings.
    ^ Cortex-M4 Specification Summary; ARM Holdings.
    ^ Cortex-R4 Specification Summary; ARM Holdings.
    ^ Cortex-R5 Specification Summary; ARM Holdings.
    ^ a b Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; January 31, 2011.
    ^ Cortex-R7 Specification Summary; ARM Holdings.
    ^ Cortex-A5 Specification Summary; ARM Holdings.
    ^ Cortex-A7 Specification Summary; ARM Holdings.
    ^ a b Deep inside ARM's new Intel killer; The Register; October 20, 2011.
    ^ Cortex-A8 Specification Summary; ARM Holdings.
    ^ Cortex-A9 Specification Summary; ARM Holdings.
    ^ Cortex-A12 Summary; ARM Holdings.
    ^ Cortex-A15 Specification Summary; ARM Holdings.
    ^ Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com
    ^ "Cortex-A53 Processor". ARM Holdings. Retrieved 2012-10-13.
    ^ "Cortex-A57 Processor". ARM Holdings. Retrieved 2012-10-13.
    ^ [1]
    ^ "3rd Generation Intel XScale Microarchitecture: Developer’s Manual". download.intel.com. Intel. May 2007. Retrieved 2 December 2010.
    ^ a b Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech.
    ^ Lal Shimpi, Anand (September 15, 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. Retrieved September 15, 2012.
    Further reading[edit source | edit]The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3. (Online Sample)
    The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN 978-1-85617-963-8. (Online Sample)

     

    [hide]v t eARM-based chips

    ARM architecture List of ARM microprocessor cores

    Application
    Processors Cortex-A5 Actions ATM7025/7029 Qualcomm Snapdragon S4 Play/200 InfoTMIC iMAPx820/iMAPx15 Telechips TCC892x

    Cortex-A7 Allwinner A20/A31s/A31 HiSilicon K3V3 Leadcore LC1813 MediaTek MT6572/6589/6589T/6589M/8125/6599 Qualcomm Snapdragon 200/400 Samsung Exynos 5410

    Cortex-A8 Allwinner A10/A13/A10s Apple A4 Freescale i.MX5x Rockchip RK290x/RK291x Samsung Exynos 3110/S5PC110/S5PV210 Texas Instruments OMAP 3 ZiiLABS ZMS-08

    Cortex-A9 Amlogic AML8726 Apple A5/A5X Freescale i.MX6x HiSilicon K3V2/K3V2T/K3V2E MediaTek MT6575/6577 Nvidia Tegra 2/3/4i Nufront NuSmart 2816M/NS115/NS115M Renesas EMMA EV2 Rockchip RK292x/RK30xx/RK31xx Samsung Exynos 4 ST-Ericsson NovaThor Telechips TCC8803 Texas Instruments OMAP 4 VIA WonderMedia WM88x0/89x0 ZiiLABS ZMS-20, ZMS-40

    Cortex-A15 HiSilicon K3V3 MediaTek MT6599 Nvidia Tegra 4 Samsung Exynos 5 Texas Instruments OMAP 5

    ARMv7-A
    compatible Apple A6/A6X (Swift) Qualcomm Snapdragon S1/S2/S3 (Scorpion) Qualcomm Snapdragon S4 Plus/S4 Pro (Krait) Qualcomm Snapdragon 600/800 (Krait 300/Krait 400) Marvell P4J


    Embedded
    Microcontrollers Cortex-M0 Energy Micro EFM32 Zero NXP LPC1100, LPC1200 STMicroelectronics STM32 F0

    Cortex-M0+ Freescale Kinetis L NXP LPC800

    Cortex-M1 Actel FPGAs Altera FPGAs Xilinx FPGAs

    Cortex-M3 Actel SmartFusion, SmartFusion 2 Atmel AT91SAM3 Cypress PSoC 5 Energy Micro EFM32 Tiny, Gecko, Leopard, Giant Fujitsu FM3 NXP LPC1300, LPC1700, LPC1800 Silicon Labs Precision32 STMicroelectronics STM32 F1, F2, L1, W Texas Instruments F28, LM3, TMS470, OMAP 4 Toshiba TX03

    Cortex-M4 Atmel AT91SAM4 Freescale Kinetis K Texas Instruments OMAP 5

    Cortex-M4F Energy Micro EFM32 Wonder Freescale Kinetis K Infineon XMC4000 NXP LPC4000, LPC4300 STMicroelectronics STM32 F3, F4 Texas Instruments LM4F


    Real-Time
    Microcontrollers Cortex-R4F Texas Instruments RM4, TMS570

    Cortex-R5F Scaleo OLEA


    Classic
    Processors ARM7 Atmel AT91SAM7, AT91CAP7, AT91M, AT91R NXP LPC2100, LPC2200, LPC2300, LPC2400, LH7 STMicroelectronics STR7

    ARMv4
    compatible Digital Equipment Corporation StrongARM

    ARM9 Atmel AT91SAM9, AT91CAP9 Freescale i.MX1x, i.MX2x Rockchip RK27xx/RK28xx NXP LPC2900, LPC3100, LPC3200, LH7A ST-Ericsson Nomadik STn881x STMicroelectronics STR9 Texas Instruments OMAP 1, AM1x VIA WonderMedia WM8505/8650 ZiiLABS ZMS-05

    ARMv5
    compatible Digital Equipment Corporation XScaleMarvell Sheeva Feroceon Jolteon Mohawk

    ARM11 Broadcom BCM2835 (Raspberry Pi) Freescale i.MX3x Infotmic IMAPX210/220 Nvidia Tegra APX, 6xx Qualcomm MSM7000, Snapdragon S1 ST-Ericsson Nomadik STn882x Telechips TCC8902 TI OMAP 2 VIA WonderMedia WM87x0

    ARMv6
    compatible Mindspeed Comcerto 1000 .

  • more infoamtion
  • The ARM architecture is licensable. Companies that are current or former ARM licensees include Advanced Micro Devices, Inc.,[11] Alcatel-Lucent, Altera, Apple Inc., AppliedMicro, Atmel, BlackBerry (formerly Research In Motion), Broadcom, Cirrus Logic, CSR plc, Cypress Semiconductor, Digital Equipment Corporation, Ember, Energy Micro, Freescale (spin-off from Motorola in 2004), Fujitsu, Fuzhou Rockchip, Huawei, Intel (through DEC), LG, Marvell Technology Group, Microsemi, Microsoft, NEC, Nintendo, Nuvoton, Nvidia, NXP (formerly Philips Semiconductor), Oki, ON Semiconductor, Panasonic, Qualcomm, Renesas, Samsung, Sharp, Silicon Labs, Sony, ST-Ericsson, STMicroelectronics, Symbios Logic, Texas Instruments, Toshiba, Yamaha, Xilinx and ZiiLABS.

    ARM offers several microprocessor core designs, including the ARM7, ARM9, ARM11, Cortex-A8, Cortex-A9, and Cortex-A15. Companies often license these designs from ARM to manufacture and integrate into their own system on a chip (SoC) with other components including RAM, GPUs or radio basebands (for mobile phones).

    System-on-chip packages integrating ARM's core designs include Nvidia Tegra's first three generations, CSR plc's Quatro family, ST-Ericsson's Nova and NovaThor, Silicon Labs's Precision32 MCU, Texas Instruments's OMAP products, Samsung's Hummingbird and Exynos products, Apple's Ax SoC line, and Freescale's i.MX.

    Companies can also obtain an ARM architectural licence for designing their own CPU cores using the ARM instruction set. Distinct ARM architecture implementations by licensees include Apple's A6, AppliedMicro's X-Gene, Qualcomm's Snapdragon and Krait, DEC's StrongARM, Marvell (formerly Intel) XScale and Nvidia's planned Project Denver.

    History[edit source | edit]Originally conceived by the British company Acorn Computers for use in its personal computers, the first ARM-based products were the co-processor modules for the BBC Micro series of computers. After achieving success with the BBC Micro computer, Acorn Computers considered how to move on from the relatively simple MOS Technology 6502 processor to address business markets like the one that would soon be dominated by the IBM PC, launched in 1981. The Acorn Business Computer (ABC) plan required a number of second processors to be made to work with the BBC Micro platform, but processors such as the Motorola 68000 and National Semiconductor 32016 were considered to be unsuitable, and the 6502 was not powerful enough for a graphics based user interface.[12]

    After testing all of the available processors and finding them lacking, Acorn decided that it needed a new architecture. Inspired by white papers on the Berkeley RISC project, Acorn considered designing its own processor.[13] A visit to the Western Design Center in Phoenix, where the 6502 was being updated by what was effectively a single-person company, showed Acorn engineers Steve Furber and Sophie Wilson they did not need massive resources and state-of-the-art research and development facilities.[14]

    Wilson developed the instruction set, writing a simulation of the processor in BBC Basic that ran on a BBC Micro with a second 6502 processor. This convinced the Acorn engineers that they were on the right track. Wilson approached Acorn's CEO, Hermann Hauser, and requested more resources. Once approval was given, a small team was assembled to implement Wilson's model in hardware.


    A Conexant ARM processor used mainly in routersAcorn RISC Machine: ARM2[edit source | edit]The official Acorn RISC Machine project started in October 1983. VLSI Technology was chosen as the "silicon partner," as they were a source of ROMs and custom chips for Acorn. The design was led by Wilson and Furber, and was consciously implemented with a similar efficiency ethos as the 6502.[15] A key design goal was achieving low-latency input/output (interrupt) handling like the 6502. The 6502's memory access architecture had allowed developers to produce fast machines without using costly direct memory access hardware. VLSI produced the first ARM silicon on 26 April 1985—it worked the first time, and was known as ARM1 by April 1985.[2] The first production systems named ARM2 were available the following year.


    The ARM1 second processor for the BBC MicroThe first practical application of the ARM was as a second processor for the BBC Micro, where it saw use developing the simulation software to finish development of the support chips (VIDC, IOC, MEMC), and to speed up the CAD software used in ARM2 development. Wilson subsequently rewrote BBC Basic in ARM assembly language, and the in-depth knowledge obtained from designing the instruction set enabled the code to be very dense, making ARM BBC Basic an extremely good test for any ARM emulator. The original aim of a principally ARM-based computer was achieved in 1987 with the release of the Acorn Archimedes.[16]

    In 1992, Acorn once more won the Queen's Award for Technology for the ARM.

    The ARM2 featured a 32-bit data bus, 26-bit address space and 27 32-bit registers. 8 bits from the program counter register were available for other purposes; the top 6 bits (available because of the 26-bit address space), served as status flags, and the bottom 2 bits (available because the program counter was always word aligned), were used for setting modes. Although the address bus was extended to 32 bits in the ARM6, program code still had to lie within the first 64 megabytes of memory in 26-bit compatibility mode, due to the reserved bits for the status flags.[17] The ARM2 had a transistor count of just 30,000, compared to Motorola's six-year-older 68000 model with 68,000.[18] Much of this simplicity came from the lack of microcode (which represents about one-quarter to one-third of the 68000) and from (like most CPUs of the day) not including any cache. This simplicity enabled low power consumption, yet better performance than the Intel 80286. A successor, ARM3, was produced with a 4 KB cache, which further improved performance.[19]

    Apple, DEC, Intel, Marvell: ARM6, StrongARM, XScale[edit source | edit]In the late 1980s Apple Computer and VLSI Technology started working with Acorn on newer versions of the ARM core. In 1990, Acorn spun off the design team into a new company named Acorn RISC Machines Ltd., which became ARM Ltd when its parent company, ARM Holdings plc, floated on the London Stock Exchange and NASDAQ in 1998.[20]

    The new Apple-ARM work would eventually evolve into the ARM6, first released in early 1992. Apple used the ARM6-based ARM 610 as the basis for their Apple Newton personal digital assistant (PDA). In 1994, Acorn used the ARM 610 as the main central processing unit (CPU) in their Risc PC computers. DEC licensed the ARM6 architecture and produced the StrongARM. At 233 MHz, this CPU drew only one watt (newer versions draw far less). This work was later passed to Intel as a part of a lawsuit settlement, and Intel took the opportunity to supplement their i960 line with the StrongARM. Intel later developed its own high performance implementation named XScale which it has since sold to Marvell.

    Licensing[edit source | edit]The ARM core has remained essentially the same size throughout these changes. ARM2 had 30,000 transistors, the ARM6 grew only to 35,000. ARM's primary business is selling IP cores, which licensees use to create microcontrollers and CPUs based on those cores. The original design manufacturer combines the ARM core with other parts to produce a complete CPU, typically one that can be built in existing semiconductor fabs at low cost and still deliver substantial performance. The most successful implementation has been the ARM7TDMI with hundreds of millions sold. Atmel has been a precursor design center in the ARM7TDMI-based embedded system.

    The ARM architectures used in smartphones, personal digital assistants and other mobile devices range from ARMv5, used in low-end devices, to ARMv6, to the Cortex A-Series (ARMv7) in current high-end devices. ARMv7 includes a hardware floating point unit, with improved speed compared to software-based floating point.

    In 2009, some manufacturers introduced netbooks based on ARM architecture CPUs, in direct competition with netbooks based on Intel Atom.[21] According to analyst firm IHS iSuppli, by 2015, ARM ICs are estimated to be in 23% of all laptops.[22]

    ARM cores[edit source | edit]Main article: List of ARM microprocessor cores
    Architecture Family designed by ARM Holdings Family designed by 3rd Party Cortex Profile
    ARMv1 ARM1
    ARMv2 ARM2, ARM3 Amber
    ARMv3 ARM6, ARM7
    ARMv4 ARM7TDMI, ARM8, ARM9TDMI StrongARM, FA526
    ARMv5 ARM7EJ, ARM9E, ARM10E XScale, FA626TE, Feroceon, PJ1/Mohawk
    ARMv6 ARM11
    ARMv6-M ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1 Microcontroller
    ARMv7-M ARM Cortex-M3 Microcontroller
    ARMv7E-M ARM Cortex-M4 Microcontroller
    ARMv7-R ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7 Real-Time
    ARMv7-A ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8,
    ARM Cortex-A9, ARM Cortex-A12, ARM Cortex-A15 Scorpion, Krait, PJ4/Sheeva, Swift Application
    ARMv8-A ARM Cortex-A53, ARM Cortex-A57[23] X-Gene, Denver Application

    A list of vendors who implement ARM cores in their design is provided by ARM.[24]

    Example applications of ARM cores[edit source | edit]Main article: List of applications of ARM cores
    ARM cores are used in a number of products, particularly PDAs and smartphones. Some computing examples are the Microsoft Surface, Apple iPad and ASUS Eee Pad Transformer. Others include the Apple iPhone smartphone, iPod portable media player, Canon PowerShot A470 digital camera, Nintendo DS handheld game console and TomTom turn-by-turn navigation system.

    In 2005, ARM took part in the development of Manchester University's computer, SpiNNaker, which used ARM cores to simulate the human brain.[25]

    ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard and other Single-board computers, because they are very small, inexpensive and consume very little power.

    Architecture[edit source | edit] This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. (March 2011)

    From 1995, the ARM Architecture Reference Manual has been the primary source of documentation on the ARM processor architecture and instruction set, distinguishing interfaces that all ARM processors are required to support (such as instruction semantics) from implementation details that may vary. The architecture has evolved over time, and starting with the Cortex series of cores, three "profiles" are defined:

    "Application" profile: Cortex-A series
    "Real-time" profile: Cortex-R series
    "Microcontroller" profile: Cortex-M series.
    Profiles are allowed to subset the architecture. For example, the ARMv6-M profile (used by the Cortex M0 / M0+ / M1) is a subset of the ARMv7-M profile which supports fewer instructions.

    CPU modes[edit source | edit]The ARM architecture specifies several CPU modes, depending on architecture. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.[26]

    User mode
    The only non-privileged mode.
    Fast Interrupt mode
    A privileged mode that is entered whenever the processor accepts an FIQ interrupt.
    Interrupt mode
    A privileged mode that is entered whenever the processor accepts an IRQ interrupt.
    Supervisor (svc) mode
    A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed.
    Abort mode
    A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
    Undefined mode
    A privileged mode that is entered whenever an undefined instruction exception occurs.
    System mode (ARMv4 and above)
    The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR.
    MON Mode (Security Extensions only)
    A monitor mode is introduced to support TrustZone extension in ARM Core.
    HYP a.k.a. PL2 Mode (ARMv7)
    A virtualization extensions / hypervisor mode in ARM Core that was introduced in latest as-of 2012 ARM-7v architecture.[27]
    Instruction set[edit source | edit]The original ARM implementation was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers.

    The ARM architecture includes the following RISC features:

    Load/store architecture.
    No support for misaligned memory accesses (although now supported since ARMv6 cores, with some exceptions related to load/store multiple word instructions).
    Uniform 16 × 32-bit register file (including the Program Counter, Stack Pointer and the Link Register).
    Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. Later, the Thumb instruction set increased code density.
    Mostly single clock-cycle execution.
    To compensate for the simpler design, compared with processors like the Intel 80286 and Motorola 68020, some additional design features were used:

    Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor.
    Arithmetic instructions alter condition codes only when desired.
    32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations.
    Powerful indexed addressing modes.
    A link register for fast leaf function calls.
    Simple, but fast, 2-priority-level interrupt subsystem with switched register banks.
    Arithmetic instructions[edit source | edit]The ARM supports add, subtract, and multiply instructions. The integer divide instructions are only implemented by ARM cores based on the following ARM architectures:

    ARMv7-M and ARMv7E-M architectures always includes divide instructions.[28]
    ARMv7-R architecture always includes divide instructions in the Thumb instruction set, but optionally in the ARM instruction set.[29]
    ARMv7-A architecture optionally includes the divide instructions. The instructions might not be implemented, or implemented only in the Thumb instruction set, or implemented in both the Thumb and ARM instructions sets, or implemented if the Virtualization Extensions are included.[29]
    Registers[edit source | edit]Registers R0-R7 are the same across all CPU modes; they are never banked.

    R13 and R14 are banked across all privileged CPU modes except system mode. That is, each mode that can be entered because of an exception has its own R13 and R14. These registers generally contain the stack pointer and the return address from function calls, respectively.

    Registers across CPU modes usr sys svc abt und irq fiq
    R0
    R1
    R2
    R3
    R4
    R5
    R6
    R7
    R8 R8_fiq
    R9 R9_fiq
    R10 R10_fiq
    R11 R11_fiq
    R12 R12_fiq
    R13 R13_svc R13_abt R13_und R13_irq R13_fiq
    R14 R14_svc R14_abt R14_und R14_irq R14_fiq
    R15
    CPSR
    SPSR_svc SPSR_abt SPSR_und SPSR_irq SPSR_fiq

    Aliases:

    R13 is also referred to as SP, the Stack Pointer.
    R14 is also referred to as LR, the Link Register.
    R15 is also referred to as PC, the Program Counter.
    Conditional execution[edit source | edit]Almost every ARM instruction has a conditional execution feature called predication, which is implemented with a 4-bit condition code selector (the predicate). To allow for unconditional execution, one of the four-bit codes causes the instruction to be always executed. Most other CPU architectures only have condition codes on branch instructions.

    Though the predicate takes up 4 of the 32 bits in an instruction code, and thus cuts down significantly on the encoding bits available for displacements in memory access instructions, it avoids branch instructions when generating code for small if statements. Apart from eliminating the branch instructions themselves, this preserves the fetch/decode/execute pipeline at the cost of only one cycle per skipped instruction.

    The standard example of conditional execution is the subtraction-based Euclidean algorithm:

    In the C programming language, the loop is:

    while (i != j)
    {
    if (i > j)
    {
    i -= j;
    }
    else
    {
    j -= i;
    }
    }

    In ARM assembly, the loop is:

    loop: CMP Ri, Rj ; set condition "NE" if (i != j),
    ; "GT" if (i > j),
    ; or "LT" if (i < j)
    SUBGT Ri, Ri, Rj ; if "GT" (Greater Than), i = i-j;
    SUBLT Rj, Rj, Ri ; if "LT" (Less Than), j = j-i;
    BNE loop ; if "NE" (Not Equal), then loop

    which avoids the branches around the then and else clauses. If Ri and Rj are equal then neither of the SUB instructions will be executed, eliminating the need for a conditional branch to implement the while check at the top of the loop, for example had SUBLE (less than or equal) been used.

    One of the ways that Thumb code provides a more dense encoding is to remove the four bit selector from non-branch instructions.

    Other features[edit source | edit]Another feature of the instruction set is the ability to fold shifts and rotates into the "data processing" (arithmetic, logical, and register-register move) instructions, so that, for example, the C statement

    a += (j << 2);

    could be rendered as a single-word, single-cycle instruction:[30]

    ADD Ra, Ra, Rj, LSL #2

    This results in the typical ARM program being denser than expected with fewer memory accesses; thus the pipeline is used more efficiently.

    The ARM processor also has features rarely seen in other RISC architectures, such as PC-relative addressing (indeed, on the 32-bit[1] ARM the PC is one of its 16 registers) and pre- and post-increment addressing modes.

    The ARM instruction set has increased over time. Some early ARM processors (before ARM7TDMI), for example, have no instruction to store a two-byte quantity.

    Pipelines and other implementation issues[edit source | edit]The ARM7 and earlier implementations have a three stage pipeline; the stages being fetch, decode and execute. Higher performance designs, such as the ARM9, have deeper pipelines: Cortex-A8 has thirteen stages. Additional implementation changes for higher performance include a faster adder, and more extensive branch prediction logic. The difference between the ARM7DI and ARM7DMI cores, for example, was an improved multiplier; hence the added "M".

    Coprocessors[edit source | edit]The ARM architecture provides a non-intrusive way of extending the instruction set using "coprocessors" which can be addressed using MCR, MRC, MRRC, MCRR, and similar instructions. The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation on processors that have one.

    In ARM-based machines, peripheral devices are usually attached to the processor by mapping their physical registers into ARM memory space or into the coprocessor space or connecting to another device (a bus) which in turn attaches to the processor. Coprocessor accesses have lower latency so some peripherals, for example an XScale interrupt controller, are designed to be accessible in both ways through memory and through coprocessors.

    In other cases, chip designers only integrate hardware using the coprocessor mechanism. For example, an image processing engine might be a small ARM7TDMI core combined with a coprocessor that has specialised operations to support a specific set of HDTV transcoding primitives.

    Debugging[edit source | edit] This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. (March 2011)

    All modern ARM processors include hardware debugging facilities, allowing software debuggers to perform operations such as halting, stepping, and breakpointing of code starting from reset. These facilities are built using JTAG support, though some newer cores optionally support ARM's own two-wire "SWD" protocol. In ARM7TDMI cores, the "D" represented JTAG debug support, and the "I" represented presence of an "EmbeddedICE" debug module. For ARM7 and ARM9 core generations, EmbeddedICE over JTAG was a de facto debug standard, although it was not architecturally guaranteed.

    The ARMv7 architecture defines basic debug facilities at an architectural level. These include breakpoints, watchpoints and instruction execution in a "Debug Mode"; similar facilities were also available with EmbeddedICE. Both "halt mode" and "monitor" mode debugging are supported. The actual transport mechanism used to access the debug facilities is not architecturally specified, but implementations generally include JTAG support.

    There is a separate ARM "CoreSight" debug architecture, which is not architecturally required by ARMv7 processors.

    Tools[edit source | edit]The ARM architecture is supported by a set of development tools such as Emprog ThunderBench for ARM. Such tools allow development engineers to program the ARM architecture device using a high level language like C.[31]

    DSP enhancement instructions[edit source | edit]To improve the ARM architecture for digital signal processing and multimedia applications, DSP instructions were added to the set.[32] These are signified by an "E" in the name of the ARMv5TE and ARMv5TEJ architectures. E-variants also imply T,D,M and I.

    The new instructions are common in digital signal processor architectures. They include variations on signed multiply–accumulate, saturated add and subtract, and count leading zeros.

    SIMD Extensions for Multimedia[edit source | edit]Introduced in ARMv6 architecture.[33]

    Jazelle[edit source | edit]Main article: Jazelle
    Jazelle DBX (Direct Bytecode eXecution) is a technique that allows Java Bytecode to be executed directly in the ARM architecture as a third execution state (and instruction set) alongside the existing ARM and Thumb-mode. Support for this state is signified by the "J" in the ARMv5TEJ architecture, and in ARM9EJ-S and ARM7EJ-S core names. Support for this state is required starting in ARMv6 (except for the ARMv7-M profile), although newer cores only include a trivial implementation that provides no hardware acceleration.

    Thumb[edit source | edit] This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. (March 2011)

    To improve compiled code-density, processors since the ARM7TDMI (released in 1994[34]) have featured Thumb instruction set, which have their own state. (The "T" in "TDMI" indicates the Thumb feature.) When in this state, the processor executes the Thumb instruction set, a compact 16-bit encoding for a subset of the ARM instruction set.[35] Most of the Thumb instructions are directly mapped to normal ARM instructions. The space-saving comes from making some of the instruction operands implicit and limiting the number of possibilities compared to the ARM instructions executed in the ARM instruction set state.

    In Thumb, the 16-bit opcodes have less functionality. For example, only branches can be conditional, and many opcodes are restricted to accessing only half of all of the CPU's general purpose registers. The shorter opcodes give improved code density overall, even though some operations require extra instructions. In situations where the memory port or bus width is constrained to less than 32 bits, the shorter Thumb opcodes allow increased performance compared with 32-bit ARM code, as less program code may need to be loaded into the processor over the constrained memory bandwidth.

    Embedded hardware, such as the Game Boy Advance, typically have a small amount of RAM accessible with a full 32-bit datapath; the majority is accessed via a 16 bit or narrower secondary datapath. In this situation, it usually makes sense to compile Thumb code and hand-optimise a few of the most CPU-intensive sections using full 32-bit ARM instructions, placing these wider instructions into the 32-bit bus accessible memory.

    The first processor with a Thumb instruction decoder was the ARM7TDMI. All ARM9 and later families, including XScale, have included a Thumb instruction decoder.

    Thumb-2[edit source | edit]Thumb-2 technology was introduced in the ARM1156 core, announced in 2003. Thumb-2 extends the limited 16-bit instruction set of Thumb with additional 32-bit instructions to give the instruction set more breadth, thus producing a variable-length instruction set. A stated aim for Thumb-2 was to achieve code density similar to Thumb with performance similar to the ARM instruction set on 32-bit memory. In ARMv7 this goal can be said to have been met.[citation needed]

    Thumb-2 extends both the ARM and Thumb instruction set with bit-field manipulation, table branches and conditional execution. A new "Unified Assembly Language" (UAL) supports generation of either Thumb-2 or ARM instructions from the same source code; versions of Thumb seen on ARMv7 processors are essentially as capable as ARM code (including the ability to write interrupt handlers). This requires a bit of care, and use of a new "IT" (if-then) instruction, which permits up to four successive instructions to execute based on a tested condition. When compiling into ARM code this is ignored, but when compiling into Thumb-2 it generates an actual instruction. For example:

    ; if (r0 == r1)
    CMP r0, r1
    ITE EQ ; ARM: no code ... Thumb: IT instruction
    ; then r0 = r2;
    MOVEQ r0, r2 ; ARM: conditional; Thumb: condition via ITE 'T' (then)
    ; else r0 = r3;
    MOVNE r0, r3 ; ARM: conditional; Thumb: condition via ITE 'E' (else)
    ; recall that the Thumb MOV instruction has no bits to encode "EQ" or "NE"

    All ARMv7 chips support the Thumb-2 instruction set. Other chips in the Cortex and ARM11 series support both "ARM instruction set state" and "Thumb-2 instruction set state".[36][37][38]

    Thumb Execution Environment (ThumbEE)[edit source | edit]ThumbEE, also termed Thumb-2EE, and marketed as Jazelle RCT (Runtime Compilation Target), was announced in 2005, first appearing in the Cortex-A8 processor. ThumbEE is a fourth processor mode, making small changes to the Thumb-2 extended Thumb instruction set. These changes make the instruction set particularly suited to code generated at runtime (e.g. by JIT compilation) in managed Execution Environments. ThumbEE is a target for languages such as Java, C#, Perl, and Python, and allows JIT compilers to output smaller compiled code without impacting performance.

    New features provided by ThumbEE include automatic null pointer checks on every load and store instruction, an instruction to perform an array bounds check, access to registers r8-r15 (where the Jazelle/DBX Java VM state is held), and special instructions that call a handler.[39] Handlers are small sections of frequently called code, commonly used to implement high level languages, such as allocating memory for a new object. These changes come from repurposing a handful of opcodes, and knowing the core is in the new ThumbEE mode.

    Thumb Execution Environment Deprecation[edit source | edit]On 23 November 2011, ARM deprecated any use of the ThumbEE instruction set.[40] This means that the Jazelle state is not supported, that is, the processor does not accelerate the execution of any Java bytecodes. Also then the processor supports ThumbEE state only to support legacy code that uses ThumbEE instructions. And lastly the BXJ instruction behaves as a BX instruction. [41]

    Floating-point (VFP)[edit source | edit] It has been suggested that ARMhf be merged into this section. (Discuss) Proposed since May 2013.

    VFP (Vector Floating Point) technology is an FPU coprocessor extension to the ARM architecture. It provides low-cost single-precision and double-precision floating-point computation fully compliant with the ANSI/IEEE Std 754-1985 Standard for Binary Floating-Point Arithmetic. VFP provides floating-point computation suitable for a wide spectrum of applications such as PDAs, smartphones, voice compression and decompression, three-dimensional graphics and digital audio, printers, set-top boxes, and automotive applications. The VFP architecture was intended to support execution of short "vector mode" instructions but these operated on each vector element sequentially and thus did not offer the performance of true single instruction, multiple data (SIMD) vector parallelism. This vector mode was therefore removed shortly after its introduction,[42] to be replaced with the much more powerful NEON Advanced SIMD unit.

    Some devices such as the ARM Cortex-A8 have a cut-down VFPLite module instead of a full VFP module, and require roughly ten times more clock cycles per float operation.[43] Other floating-point and/or SIMD coprocessors found in ARM-based processors include FPA, FPE, iwMMXt. They provide some of the same functionality as VFP but are not opcode-compatible with it.

    VFPv1 is obsolete.
    VFPv2 is an optional extension to the ARM instruction set in the ARMv5TE, ARMv5TEJ and ARMv6 architectures.
    VFPv3-D32 is broadly compatible with VFPv2 but adds exception-less FPU usage, has 32 64-bit FPU registers as standard, adds VCVT instructions to convert between scalar, float and double, adds immediate mode to VMOV such that constants can be loaded into FPU registers.
    VFPv3-D16: as above, but it has only 16 64-bit FPU registers.
    VFPv3-F16 is uncommon; it supports IEEE754-2008 half-precision (16-bit) floating point.
    VFPv4 in/for Cortex-A5, has a fused multiply-accumulate.
    Advanced SIMD (NEON)[edit source | edit]The Advanced SIMD extension (aka NEON or "MPE" Media Processing Engine) is a combined 64- and 128-bit single instruction multiple data (SIMD) instruction set that provides standardized acceleration for media and signal processing applications. NEON is included in all Cortex-A8 devices but is optional in Cortex-A9 devices.[44] NEON can execute MP3 audio decoding on CPUs running at 10 MHz and can run the GSM adaptive multi-rate (AMR) speech codec at no more than 13 MHz. It features a comprehensive instruction set, separate register files and independent execution hardware.[45] NEON supports 8-, 16-, 32- and 64-bit integer and single-precision (32-bit) floating-point data and SIMD operations for handling audio and video processing as well as graphics and gaming processing. In NEON, the SIMD supports up to 16 operations at the same time. The NEON hardware shares the same floating-point registers as used in VFP. Devices such as the ARM Cortex-A8 and Cortex-A9 support 128-bit vectors but will execute with 64 bits at a time,[43] whereas newer Cortex-A15 devices can execute 128 bits at a time.

    Security Extensions (TrustZone)[edit source | edit]The Security Extensions, marketed as TrustZone Technology, is found in ARMv6KZ and later application profile architectures. It provides a low cost alternative to adding an additional dedicated security core to an SoC, by providing two virtual processors backed by hardware based access control. This enables the application core to switch between two states, referred to as worlds (to reduce confusion with other names for capability domains), in order to prevent information from leaking from the more trusted world to the less trusted world. This world switch is generally orthogonal to all other capabilities of the processor, thus each world can operate independently of the other while using the same core. Memory and peripherals are then made aware of the operating world of the core and may use this to provide access control to secrets and code on the device.

    Typical applications of TrustZone Technology are to run a rich operating system in the less trusted world, and smaller security-specialized code in the more trusted world (named TrustZone Software, a TrustZone optimised version of the Trusted Foundations Software developed by Trusted Logic Mobility), allowing much tighter digital rights management for controlling the use of media on ARM-based devices,[46] and preventing any unapproved use of the device. Trusted Foundations Software was acquired by Gemalto. Giesecke & Devrient developed a rival implementation named Mobicore. In April 2012 ARM Gemalto and Giesecke & Devrient combined their Trustzone portfolios into a joint venture Trustonic.[47][48] Open Virtualization is an open source implementation of the trusted world architecture for TrustZone.[49]

    In practice, since the specific implementation details of TrustZone are proprietary and have not been publicly disclosed for review, it is unclear what level of assurance is provided for a given threat model.

    No-execute page protection[edit source | edit]As of ARMv6, the ARM architecture supports no-execute page protection, which is referred to as XN, for eXecute Never.[50]

    ARMv8 and 64-bit[edit source | edit]Released in late 2011, ARMv8 represents a fundamental change to the ARM architecture. It adds a 64-bit architecture, dubbed 'AArch64', and a new 'A64' instruction set. Within the context of ARMv8, the 32-bit architecture and instruction set are referred to as 'AArch32' and 'A32', respectively. The Thumb instruction sets are referred to as 'T32' and have no 64-bit counterpart. ARMv8 allows 32-bit applications to be executed in a 64-bit OS, and for a 32-bit OS to be under the control of a 64-bit hypervisor.[1] Applied Micro, AMD, Broadcom, Calxeda, HiSilicon, Samsung, ST Microelectronics and other companies have announced implementation plans.[51][52][53][54] ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012.[23]

    To both AArch32 and AArch64, ARMv8 makes VFPv3/v4 and advanced SIMD (NEON) standard. It also adds cryptography instructions supporting AES and SHA-1/SHA-256.

    AArch64 features:

    New instruction set, A64
    Has 31 general-purpose 64-bit registers.
    Separate dedicated SP and PC.
    Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped).
    Most instructions can take 32-bit or 64-bit arguments.
    Addresses assumed to be 64-bit.
    Advanced SIMD (NEON) enhanced
    Has 32 × 128-bit registers (up from 16), also accessible via VFPv4.
    Supports double-precision floating point.
    Fully IEEE 754 compliant.
    AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers.
    A new exception system
    Fewer banked registers and modes.
    Memory translation from 48-bit virtual addresses based on the existing LPAE, which was designed to be easily extended to 64-bit
    OS support:

    Linux – patches adding ARMv8 support have been posted for review by Catalin Marinas of ARM Ltd. The patches have been included in Linux kernel version 3.7 in late 2012.[55]
    ARM licensees[edit source | edit] This section needs additional citations for verification. Please help improve this article by adding citations to reliable sources. Unsourced material may be challenged and removed. (March 2011)

    Die of a STM32F103VGT6 ARM Cortex-M3 microcontroller with 1 megabyte flash memory, 72 MHz Central Processing Unit (CPU), motor control, Universal Serial Bus (USB) and Controller Area Network (CAN). Manufactured by STMicroelectronics.ARM Ltd does not manufacture or sell CPU devices based on its own designs, but rather, licenses the processor architecture to interested parties. ARM offers a variety of licensing terms, varying in cost and deliverables. ARM provides to all licensees an integratable hardware description of the ARM core as well as complete software development toolset (compiler, debugger, software development kit) and the right to sell manufactured silicon containing the ARM CPU.

    Fabless licensees, who wish to integrate an ARM core into their own chip design, are usually only interested in acquiring a ready-to-manufacture verified IP core. For these customers, ARM delivers a gate netlist description of the chosen ARM core, along with an abstracted simulation model and test programs to aid design integration and verification. More ambitious customers, including integrated device manufacturers (IDM) and foundry operators, choose to acquire the processor IP in synthesizable RTL (Verilog) form. With the synthesizable RTL, the customer has the ability to perform architectural level optimisations and extensions. This allows the designer to achieve exotic design goals not otherwise possible with an unmodified netlist (high clock speed, very low power consumption, instruction set extensions, etc.). While ARM does not grant the licensee the right to resell the ARM architecture itself, licensees may freely sell manufactured product such as chip devices, evaluation boards, complete systems. Merchant foundries can be a special case; not only are they allowed to sell finished silicon containing ARM cores, they generally hold the right to re-manufacture ARM cores for other customers.

    ARM prices its IP based on perceived value; lower performing ARM cores typically have lower licence costs than higher performing cores. In implementation terms, a synthesizable core costs more than a hard macro (blackbox) core. Complicating price matters, a merchant foundry which holds an ARM licence, such as Samsung and Fujitsu, can offer reduced licensing costs to its fab customers. In exchange for acquiring the ARM core through the foundry's in-house design services, the customer can reduce or eliminate payment of ARM's upfront licence fee. Compared to dedicated semiconductor foundries (such as TSMC and UMC) without in-house design services, Fujitsu/Samsung charge two- to three-times more per manufactured wafer.[citation needed] For low to mid volume applications, a design service foundry offers lower overall pricing (through subsidisation of the licence fee). For high volume mass-produced parts, the long term cost reduction achievable through lower wafer pricing reduces the impact of ARM's NRE (Non-Recurring Engineering) costs, making the dedicated foundry a better choice.

    Many semiconductor or IC design firms hold ARM licences: Analog Devices, AppliedMicro, Atmel, Broadcom, Cirrus Logic, Energy Micro, Faraday Technology, Freescale, Fujitsu, Intel (through its settlement with Digital Equipment Corporation), IBM, Infineon Technologies (Infineon XMC4000 32bit mcu family), Marvell Technology Group, MediaTek, Nintendo, Nvidia, NXP Semiconductors, OKI, Qualcomm, Samsung, Sharp, STMicroelectronics and Texas Instruments are some of the many companies who have licensed the ARM in one form or another.

    ARM architectural licence[edit source | edit]Not only is an ARM architectural licence much more costly, a licensee also requires the necessary engineering power to design a CPU based on the instruction set. Fewer companies have an ARM architectural licence like Intel (DEC), Marvell, Qualcomm and Broadcom.[56]

    Approximate licensing costs[edit source | edit]ARM's 2006 annual report and accounts state that royalties totalling £88.7 million were the result of licensees shipping 2.45 billion units.[57] This is equivalent to £0.036 per unit shipped. This is averaged across all cores, including expensive new cores and inexpensive older cores.

    In the same year ARM's licensing revenues for processor cores were £65.2 million,[58] in a year when 65 processor licences were signed,[59] an average of £1 million per licence. Again, this is averaged across both new and old cores.

    Given that ARM's 2006 income from processor cores was approximately 60% from royalties and 40% from licenses, ARM makes the equivalent of £0.06 per unit shipped including both royalties and licences. However, as one-off licences are typically bought for new technologies, unit sales (and hence royalties) are dominated by more established products. Hence, the figures above do not reflect the true costs of any single ARM product.

 
 
 
     
 
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